1. Field of the Invention
The present invention generally relates to a semiconductor device, and more particularly, to a semiconductor device in which an I/O circuit is formed on a semiconductor chip.
2. Description of the Prior Art
In recent electronic devices, downsizing such as miniaturization and weight reduction are rapidly being performed. To achieve this downsizing, a semiconductor device, which is a component of the electronic devices, is also miniaturized and is integrated to a high density.
With respect to, for example, a microprocessor as the semiconductor device, the microprocessor is constructed such that logic circuits, memory circuits, and input and output (I/O) circuits, etc., are installed on a semiconductor chip.
Therefore, to miniaturize the semiconductor device, there is a need for an efficient layout of such circuits on the semiconductor chip.
FIG. 1 shows an overall configuration of a conventional semiconductor device, and FIG. 2 shows a schematic configuration of areas (I/O circuit area) where I/O circuits of the conventional semiconductor device are installed.
A semiconductor device 1 shown in FIG. 1 may be, for example, the microprocessor. This semiconductor device 1 is constructed such that a logic circuit 2, a memory circuit 3, and an I/O circuit 4, etc., are installed on a semiconductor chip 5. As shown in FIG. 2, the I/O circuit 4 is constructed such that I/O cell circuits 6 for an input and an output, bonding pads 7 for input and output ports, power-source lines V.sub.DD, V.sub.SS, etc., are formed on the semiconductor chip 5.
The I/O circuit 4 is formed near sides of the semiconductor device 1, and the logic circuit 2 and the memory circuit 3 are arranged to be surrounded by this I/O circuit 4. The I/O cell circuits 6 constructing the I/O circuit 4 process to input and to output several signals to/from the logic circuit 2 and the memory circuit 3. The bonding pads 7 are wire-connected with leads 8, and are for coupling with external circuits, which are to be connected to the semiconductor chip 1, via wires and the leads 8. Further, the power-source lines V.sub.DD, V.sub.SS supply a power source to the I/O cell circuits 6, and are arranged, for example, in a form of rings in the I/O circuit area 4 of FIG. 1.
In such a conventional device, a plurality of the I/O cells 6 are arranged according to a number of routing lines which are routed to/from the logic circuits 2 and the memory circuits 3. And a number of bonding pads 7 corresponds to a number of the I/O cell circuits 6 and the power-source lines V.sub.DD, V.sub.SS. In other words, for one I/O cell circuit 6, an associated bonding pad 7 is formed to be connected with the I/O cell circuit 6. Further, the bonding pads 7 include power-source pads 7a and 7b, which may be connected with the power-source lines V.sub.DD, V.sub.SS, respectively. And the bonding pads 7 are arranged outside the I/O cell circuits 6.
However, in such a conventional configuration, such that the plurality of the bonding pads 7 are arranged in a single line only outside the I/O cell circuits 6, when the number of the bonding pads 7 are increased according to an increase of a number of pins due to a high-density integration of the semiconductor device 1, a large area for forming such a large number of bonding pads is necessary outside the I/O cell circuits 6. There is thus a problem of a size-increasing of the semiconductor device 1.
As one means to solve this problem, a configuration as shown in FIG. 3 is known. FIG. 3 shows a modified configuration of the I/O cell circuits 6 and the bonding pads 7, where the bonding pads 7 are arranged in a plural number of lines outside the I/O cell circuits 6. In FIG. 3, for example, the bonding pads 7 are arranged in a form of 4 lines.
However, in this configuration, an interval length between drawing lines 11 which are lead from the bonding pads 7 to the I/O cell circuits 6 becomes narrow, so that there is a problem that fine drawing lines 11 have to be formed.
When the drawing lines 11 are finely structured, impedance performance is degraded and parasitic capacitances are generated. These results lead to a degradation of signal transmission performance. Further, in drawing lines 11 which are connected with the power-source pads 7a and 7b, a large voltage reduction occurs, so that there are also problems of an increase in power consumption and a danger of circuit trouble.
FIG. 4 shows a conventional connecting configuration between the power-source pads 7a, 7b and the power-source lines V.sub.DD, V.sub.SS. As shown in FIG. 4, the power-source pads 7a, 7b are arranged in the single line outside the I/O cell circuits. In this case, though the power-source pad 7a may be directly connected with the power-source line V.sub.SS, the power-source pad 7b has to be connected with the power-source line V.sub.DD over the power-source line V.sub.SS.
To achieve this connection, in a prior art, first a conductive line 12 with vias 14, 15 is formed over the power-source line V.sub.SS on which an insulating film is previously formed, next, the power-source pad 7b and the power-source line V.sub.DD are connected to the conductive line 12 through the vias 15, 14, so that a pass between the power-source pad 7b and the power-source line V.sub.DD becomes conductive.
However, in such a connecting configuration, electrical resistances in the vias 14, 15 are large, whereby large voltage reductions occur in the vias 14, 15, so that there are also problems of the increase of power consumption and the danger of circuit trouble.
Furthermore, in the conventional semiconductor device 1, the I/O cell circuit 6 occupies a large-size area, and this also makes the semiconductor device large. A description of the reason for this will be given as follows.
As shown in FIG. 2, the I/O cell circuit 6 comprises a transistor part 9 in which a large number of transistors are integrated, and an I/O controller part 10. In the I/O cell circuit 6, the transistor part 9 occupies a larger area than that of the I/O controller part 10. The reason for this is as follows. An area of the transistor part 9 is associated with a number of the transistors to be formed in the chip, and the number of the transistors is based on an amount of a driving current for an input-and-output processing. And to evaluate performance of the transistor part 9, a maximum value of the driving current which may be expected is generally referenced. Therefore, a size of the transistor part 9 is increased.
And in the conventional device, each I/O cell circuit 6 is constructed in the same configuration, thus each configuration of the transistor parts 9 is also the same. Therefore, a plurality of large-sized I/O cell circuits 6 are installed on the semiconductor chip 5, so that this also leads to a size-increasing of the semiconductor device 1.
Further, as mentioned above, the transistor part 9 is evaluated by referring to the maximum value of the driving current which may be expected. However, in the plurality of I/O cell circuits 6, there are some circuits in which the input-and-output processing of the signals may be performed by a smaller driving current than the referenced maximum value. In such I/O cell circuits, several transistors of the transistor part 9 are not utilized for the input-and-output processing. Therefore, an area occupied by unutilized transistors may be a useless space producing an inefficient integration of the semiconductor device.